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Output Functions and Hierarchical Design States

 

Feature Description

 
When there are hierarchical states on an assembly, hierarchical functions are created differently on that assembly. Normally, for each port on an assembly, either a single output function is created (when the port corresponds to a lower-level output flag whose visibility is set to "Single Output") or an upper-level output function is created for each lower-level net function on the net connected to the lower-level flag (when the flag's visibility is set to "Multiple Output"). For assemblies with hierarchical states, however,   creates multiple instances of each output function—one for each lower-level design state that is upstream from the associated lower-level output flag. The possibilities are enumerated in the following table:
 

Hierarchical Design State Settings Explained

 
Settings on Lower-Level
Output Flag
Number of Upstream
Design States
Resulting Output Function(s) on Assembly
Visibility set to "Single Output"
one or fewer
one
more than one
one per upstream design state
Visibility set to "Multiple Output"
(single input port on flag)
one or fewer
one per net function on the net connected to the lower-level output flag
more than one
one per net function / design state pair
Visibility set to "Multiple Output"
(multiple input ports on flag)
one or fewer
one per input port on lower-level output flag
more than one
one per input port / design state pair
 
When multiple output functions are created on an assembly port due to the existence of multiple upstream design states, then the corresponding design state name will be appended to the usual function name (e.g., "OBJECT - PORT{[Design State 1]}").
 
Warning: Because the number of output functions created on an assembly port is based on the number of related (upstream) lower-level design states, the Analyst should be extremely careful when an assembly is linked to a lower-level design that contains a large number of design states. This is particularly important for designs in which thousands of design states have been generated automatically using the Auto-Create operation. The Analyst should also be careful when a large number of net functions propagate into an output flag whose Visibility is set ot "Multiple Output"—if there are, for example, five design states upstream from that flag, then the upper-level assembly port would have five times as many output functions as there are lower-level net functions appearing at that flag. It is up to the Analyst to ensure that an unmanageably large number of output functions are not created due to unnecessary design states in the lower-level model. For further details related to this issue, please refer to the topics "The Dangers of Using Design States" and "Good Design State Practices".