Although design states offer some powerful capabilities, they should nevertheless be used with extreme caution. The indiscriminate use of design states can significantly increase the time it takes to develop models or generate diagnostic analysis. Furthermore, the incorrect use of design states can result in incomplete functional capture at upper design levels (thereby causing analysis results to be inaccurate). The three main dangers associated with design states are as follows:
Modeling Slow-Down - When a design contains large numbers of design states, it can impact the speed in which some operations are able to be performed. For example, if a design were to contain 20,000 automatically-generated design states and the Analyst were to enable mutually-exclusive states for a single object, the software may take several minutes to update all design states so that no more than one state of that object is enabled at a time.
Excessive Output Functions - When a large number of design states are inherited hierarchically, it can dramatically increase the number of functions defined on the corresponding upper-level assemblies—especially if the lower-level design uses "Multiple Output" I/O flags (for a detailed discussion of this issue, refer to the topic "Output Functions and Hierarchical States"). In many cases, the unchecked inheritance of automatically-generated design states will result in many more output functions than are necessary to achieve the desired diagnostic resolution. This can have a significant impact on the amount of time it takes to generate diagnostic analysis, as well as the overall "understandability" of analysis results.
Incomplete Function Definitions - When design states are inherited hierarchically, upper-level functions are created based on the specific design states that are visible at each upper-level port (see "Output Functions and Hierarchical States" for more details). If there are lower-level output functions that reside along a state-controllable path, yet are not included in any of the hierarchically-inherited design states, then they will not be "children" of any of the upper-level output functions that are created on the linked assembly. This is tantamount to saying that the lower-level function is not used within the upper-level system. Because eXpress analyses automatically exclude unused functions, incomplete sets of lower-level design state definitions can result in inaccurate analysis results if those states are inherited into higher design levels.
Invalid State Configurations - When the Analyst creates design states using the Auto-Create operation, it is possible that some of the design states represent invalid state configurations—that is, combinations of object states that would either not be possible, or would not present themselves given the system's concept of operations. The Analyst must either remove all invalid design state definitions or ensure that the design is set up in a manner that will prevent invalid design states from being generated. If diagnostic analysis is performed using invalid state configurations, the resulting assessments may inaccurately reflect the diagnostic capability of the design.
Fortunately, with a little care, the Analyst can usually avoid the pitfalls of using design states (for a list of ways in which the Analyst can mitigate the dangers of using design states, please refer to the discussion of "Good Design State Practices").
